(1) FIELD OF THE INVENTION
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of ion implantation which prevents electrical charge damage to the device structures of the integrated circuit.
(2) DESCRIPTION OF THE PRIOR ART
Conventional high-dose ion implantation is performed after a thin oxide formation, the purpose of which is to avoid ion channeling effects as well as in-process contamination. Such protective layers are described in U.S Pat. No. 5,061,644 to Jerry Yue et al U.S. Pat. No. 5,037,767 P.J Daniel describes ion implantation through a resist layer U.S. Pat. No. 5,030,57 to Calviello uses a mask of preferably silicon oxide.
The implanted ions are always charged so that they can be accelerated to the appropriate energies before reaching the wafers. However, the charging on the gate polysilicon electrode causes an enormous electrical field on the gate dielectric silicon oxide which can result in damage to the gate dielectric silicon oxide, a non-uniform dose of ions across the wafer, dosage accuracy problems, and "explosion" of photoresist masking layer.
For example, a typical source/drain (S/D) implant dose is 2 to 7.times.10.sup.15 per cm.sup.2 and a typical gate oxide thickness is less than 200 Angstroms for devices with submicron feature sizes. During the S/D implantation, the gate polysilicon is isolated by the gate oxide and spacers from the grounded substrate. The electrical field across the gate oxide can be derived as follows: EQU V=Q/C
where V is the voltage, Q is the charge, and C is the capacitor. EQU C=(4 pi ee.sub.o A)/t.sub.ox
where ee.sub.o is the dielectric constant of oxide, A is the gate area, and t.sub.ox is the gate dielectric silicon oxide thickness. Then, the electrical field (E) across the gate dielectric silicon oxide will be EQU E=V/t.sub.ox
and then EQU E=Q/(4 pi ee.sub.o A)
Substituting the parameters into the formulas, Q/A=1.6.times.10.sup.-19 Coul.times.5.times.10.sup.15 /cm.sup.2, ee.sub.0 =3.9.times.8.85.times.10.sup.-14 F/cm, and F=Coul/Volt, the result is: EQU E=1.84.times.10.sup.8 Volt/cm=184 MV/cm.
This value is much higher than the gate dielectric silicon oxide can endure. The normal breakdown field for a gate dielectric silicon oxide is less than 20 MV/cm. This huge electric field will cause serious damage to the gate oxide even if there is some thermal recovery process after ion implantation. In an effort to resolve the charging problem, an electron "flood gun" has been used during ion implantation to neutralize the ions before their arrival at the wafer. However, the "flood gun" cannot neutralize all the ions and some charge damages still occur.